The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, normally of monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening through the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric interlayer can be removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line. In U.S. Pat. No. 5,635,423, prior art single and dual damascene techniques are disclosed, in addition to several improved dual damascene techniques for simultaneously forming a conductive line in electrical contact with a conductive plug for greater accuracy in forming fine line patterns with minimal interwiring spacings
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit.
If the interconnection node is routed over a considerable distance. e.g.. hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules. e.g.. a design rule below about 0.18.mu., the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching or by damascene techniques wherein trenches are formed in dielectric layers and filled with a conductive material. Excess conductive material on the surface of the dielectric layer is then removed by CMP. Al is conventionally employed because it is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems have arisen involving the use of Al which has decreased the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyimide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al.
One approach to improved interconnection paths in vias comprises the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for a wiring metal and W plugs for interconnections at different levels. However, the use W is attendant with several disadvantages. For example, most W processes are complex and expensive. Moreover, W has a high resistivity. The Joule heating may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation and the interface with the wiring layer usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem comprises the use of chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures for Al deposition. The use of CVD for depositing Al has proven expensive, while hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Cu and Cu alloys have recently received considerable attention as a replacement material for Al in VLSI interconnection metallizations. Cu has a lower resistivity than Al, and has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, it is difficult to form void free Cu or Cu alloy interconnects with high electromigration resistance. There are additional disadvantages attended upon the use of Cu or Cu alloys. For example, Cu is easily oxidized and vulnerable to corrosion.
One conventional approach in attempting to form Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Chow et al., U.S. Pat. No. 4,789,648. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride (Si.sub.3 N.sub.4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
The difficulty of forming voidless interconnects is particular acute in damascene technology. For example, adverting to FIG. 1, an opening in dielectric layer 10 is filled with copper 11 to form a via/contact 11. The damascene opening can be filled by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating or electroless plating. Although not depicted for illustrative convenience, a barrier layer is typically formed in the opening prior to Cu metallization. Via 11 forms an electrical interconnection with underlying metal feature 12. In the case of contact 11, the underlying feature would be a source/drain region on a semiconductor substrate. As shown in FIG. 1, a void 13 is typically formed in via/contact 11. A conventional approach to this problem comprises heat treating at atmospheric pressure in a furnace or chamber at a temperature of about 80.degree. C. to about 400.degree. C. Such heat treatment is performed to alter the grain size and orientation of the Cu metallization to anneal out voids due to crystal growth and, hence, improve electromigration resistance.
It was, however, found that voids 14 would form at the sides of the opening, as shown in FIG. 2. It is believed that such voids 14 occur as a result of the migration of Cu atoms to fill the void 13 (FIG. 1), proximate the center of the via/contact 11. Accordingly, there exists a need for void free Cu metallization technology. There exists a particular need for methodology to implement void free Cu or Cu alloy damascene interconnect patterns.